1. Field of the Invention
The invention relates to a semiconductor device, and more particularly to a switching transistor and a capacitor for use in a memory cell of a dynamic random access memory (DRAM).
2. Description of the Prior Art
With a demand today for higher integration of DRAM, various attempts have been made to reduce the area of memory cells. For instance, Japanese Unexamined Patent Public Disclosure No. 63-240061 laid open on Oct. 5, 1988 has suggested a semiconductor device in which a diffusion layer capacitor electrode is formed in a trench formed with a semiconductor device to thereby provide a smaller memory cell area.
Hereinbelow will be explained the semiconductor device suggested in No. 63-240061 with reference to FIGS. 1 and 2, in which FIG. 1 is a cross-sectional view of a memory cell of DRAM, and FIG. 2 is a top plan view. As illustrated, a p-type Si substrate 24 is formed with trenches, along an inner surface of which is formed an n-type diffusion layer 25 and an oxide layer 26 over the n-type diffusion layer 25. Each of the trenches are filled with a plate electrode 23. The n-type diffusion layer 25, the oxide layer 26 and the plate electrode 23 define a cell capacitor. The cell capacitor is isolated from adjacent cell capacitors by a heavily doped p-type diffusion layer 33 formed at the bottom of each of the trenches. A switching transistor comprises a vertical type MOS field effect transistor (FET) composed of an n-type source layer 29 deposited on an exposed end portion of the n-type diffusion layer 25, a p-type channel layer 32 deposited on the n-type source layer 29, and an n-type drain layer 31 deposited on the p-type channel layer 32. These layers 29, 32, 31 are formed by selective epitaxial growth. Thus, a channel 30 extends vertically to the Si substrate 24.
As mentioned later with reference to FIG. 3D, a gate oxide layer 39 is formed along a side wall of epitaxial layers 36, 37 and 38. Writing a charge to the cell capacitor and reading a charge from the cell capacitor is carried out by applying a voltage to gate electrode 27 of the switching transistor. The epitaxial layers 29, 31 and 32 and the Si substrate 1 are covered with an interlayer insulating film 41, on which bit lines 28 extend. The bit lines 28 are in contact with associated n-type drain layers 31 through the interlayer insulating film 41. Over the bit lines 28 is deposited a passivation layer 34.
Hereinbelow will be explained a method for fabricating the above mentioned semiconductor device with reference to FIGS. 3A to 3E. First, as illustrated in FIG. 3A, the p-type Si substrate 24 is formed with a plurality of trenches (no reference numeral). Then, at the bottom of each of the trenches is formed a heavily doped p-type diffusion region serving as a channel stopper 33, and along an inner side wall of each of the trenches is formed the n-type diffusion layer 25. After the n-type diffusion layer 25 and the channel stopper 33 has been covered with the oxide layer 26, each of the trenches is filled with polysilicon by evaporation to thereby form the plate electrode 23.
Then, an oxide layer 35 is deposited all over the Si substrate 24. As illustrated in FIG. 3B, the oxide layer 35 is patterned by means of wet etching so that there are exposed only areas in which a memory cell transistor is to be formed. After preparation such as washing, the Si substrate 24 is placed into a molecular beam epitaxy (MBE) apparatus, in which a layer 36 including As, a layer 37 including B, and a layer 38 including As are epitaxially grown in this order on the substrate 24 at a substrate temperature in the range of 700 to 800 degrees centigrade.
Thus, layers 36a are selectively, epitaxially grown on the above mentioned area at which the Si substrate 24 is exposed, while the Si layer becomes a polysilicon layer on the oxide layer 35. Then, the Si substrate 24 is etched with boiled nitric acid to thereby remove only the polysilicon layer and leave the epitaxial layers 36a as they are, as illustrated in FIG. 3C. Then, as illustrated in FIG. 3D, the Si substrate 24 is oxidized to thereby form a gate oxide layer 39 on the Si substrate 24 and along side walls of the epitaxial layers 36a. Thereinafter, material for electrode formation is deposited and patterned to thereby form gate electrodes 40 along the side wall of the epitaxial layers 36a on 5 the gate oxide layer 39.
Then, as illustrated in FIG. 3E, an interlayer insulating layer 41 is deposited over the Si substrate 24 and the epitaxial layers 36a, and is flattened. Over the flattened interlayer insulating layer 41 is deposited a second interlayer insulating layer 42. Then, there are formed contact windows reaching the e-type drain layer 31 of the epitaxial layers 36a through the interlayer insulating layers 41 and 42. Then, as illustrated in FIG. 1, the bit lines 28 are formed over the second interlayer insulating layer 42. Finally, over the bit lines 28 is deposited the passivation layer 34. Thus, a memory cell as illustrated in FIG. 1 is completed.
As is obvious based on the above description with reference, in particular, to FIG. 1, in the prior art method, a memory cell transistor is formed on the n-type diffusion layer 25 serving as a capacitor electrode in a vertical arrangement, and hence there is no area in which the memory cell transistor overlaps the cell capacitor composed of the n-type diffusion layer 25, the oxide layer 26, and the plate electrode 23. Thus, it is possible to reduce the cell area, though the flatness of the Si substrate is degraded.
However, the above mentioned prior art memory cell structure for a semiconductor device poses problems with respect to its structure, fabrication technologies, and fabrication cost, as follows.
One of structural problems is that a switching transistor is stacked on a semiconductor substrate so that a channel extends perpendicularly to the semiconductor substrate. This reduces memory cell area, but at the same time degrades the flatness of the semiconductor substrate. The degradation of the flatness of the semiconductor substrate makes subsequent lithography and metallization more difficult. The degree of such difficulty is markedly increased with the reduction of the memory cell design rule.
The structural advantage of a trench capacitor cell relative to a stacked capacitor cell is that substrate flatness is not degraded because the capacitor does not have a stack-up structure but rather has a dig-down structure. However, the above mentioned prior art method and device reduces the advantage of the trench capacitor cell.
Regarding memory cell area, a bit line contact, a word line and an element isolation cannot be designed smaller than the size allowed by the design rule. Hence, even in an open bit line structure as illustrated in FIG. 2, the cell area cannot be designed to be smaller than 6F.sup.2 wherein F represents the design rule. In spite of an increased number of fabrication steps, the value 6F.sup.2 remains the same minimum size value obtained when the memory cell is composed of a flat type transistor.
In addition, in the prior art device, if the epitaxial layers are not formed precisely in a square as viewed from the top, the thickness of the gate oxide layer formed through gate oxidation becomes nonuniform because the side wall of the epitaxial layers have crystal orientations different depending on the area of the side wall. Consequently, when the memory cell transistor is driven, the channel current is concentrated to a portion having a thinner gate oxide layer than other portions, thereby reducing the reliability or life span of the gate oxide layer. Furthermore, since the substrate of the memory cell transistor is in a floating condition, it is impossible to control the substrate potential.
A problem with respect to fabrication technologies is that the alignment margin is strictly limited in the lithography step for opening windows within the oxide layer 35, on which windows the epitaxial layers 36a are to be formed (see FIG. 3B). If the window for the epitaxial layers 36a is formed out of place overlapping the trench, the source 29 of the memory cell transistor is short-circuited with the plate electrode 23, that is, the capacitor electrode is short-circuited with the plate electrode 23.
On the other hand, if the window for the epitaxial layers 36a is formed out of place closer to the device region 2, the source 29 of the memory cell transistor will not overlap an exposed portion of the n-type diffusion layer 25, and thereby the switching transistor will be isolated from the cell capacitor. Accordingly, the alignment margin in the lithography step is equal at most to half of a thickness of the n-type diffusion layer 25 formed along an inner side wall of the trench. Since the alignment is carried out not to a surface of a diffusion layer but to a thickness of a diffusion layer, it is unavoidable that the alignment margin is small.
A problem with respect to fabrication cost is in the selective growth step by means of molecular beam epitaxy. Molecular epitaxy is characterized by low temperature growth, and has relatively good controllability with respect to crystal growth speed. Hence, it is possible to provide a properly controlled epitaxial structure, if accuracy in concentration of impurities is not required. However, molecular epitaxy needs an apparatus capable of achieving an ultra-high vacuum, with the result of high apparatus cost and low throughput. In addition, the addition of a selective epitaxial growth step increases fabrication cost. Accordingly, molecular epitaxy is not suitable for DRAM fabrication requiring larger production capacity and lower cost.
Furthermore, the above mentioned difficulties in fabrication technologies decrease fabrication yield and thereby increase fabrication cost. Based on the foregoing, if a flat type transistor can be provided in much the same area as other types of transistors, it is more advantageous to compose a memory cell of a flat type transistor, so that the channel impurities profile in the cell transistor, the source/drain impurities profile, and the thickness of the gate insulating film can be readily controlled.